1. Field of the Invention
The present invention relates to integrated circuit package assembly.
2. Background Art
Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to circuit board. One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. One type of BGA package has one or more IC dies attached to a first surface of a package substrate, and has an array of solder ball pads located on a second surface of the package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to a circuit board.
An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are mounted directly to the IC die when the IC die has not yet been singulated from its fabrication wafer. As such, wafer-level BGA packages do not include a package substrate. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.
For IC dies used in wafer-level BGA packages, routing is typically formed directly on the dies. The routing is formed on a surface of the dies to route signals of the die pads to locations where the solder balls attach to the die. Fan-in routing and fanout routing are two different types of routing that may be formed on the dies. Fan-in routing is a type of routing that is formed only within the area of each semiconductor die. Fanout routing is a type of routing that extends outside of the areas of the semiconductor dies. For instance, for each die, a material may be applied around the area of die semiconductor material, and the applied material is solidified. Fanout routing may then be applied to the die that extends over the applied material beyond the area of the die. As such, fanout routing provides advantages, including enabling routing to be performed over a larger area, providing more room for signal traces. However, current fanout routing technology requires very heavy capital investment. Such capital investment does not provide cost benefits in the short run, although such investment may provide cost competitiveness in the long run. Furthermore, the current fanout routing technology is constrained with respect to capacity, due to the current trend in the industry to migrate more and more devices into wafer level packaging. As such, while the cost of fanout wafer-level manufacturing is decreasing, it has been difficult for fanout wafer-level manufacturing to keep up with the increasing pressure to reduce prices and to maintain profit margins.